Publication | 论文发表
☐ Prof.Rongmei Chen has published more than 60 international journal articles and conference papers, including Nature Electronics and IEEE series;
☐ 14 journal articles are published by Prof.Chen as the first author or corresponding author in the field of microelectronics and integrated circuits, including 1 on Nature Electronics, 2 on IEEE Transactions on Electron Devices, 2 on IEEE Transactions on Very Large Scale Integration Systems, 6 on IEEE Transactions on Nuclear Science (a top journal in the field of integrated circuit radiation effects), and 3 on Microelectronics Reliability (a well-known journal in the field of microelectronics reliability); 13 co-authored SCI journal articles are not listed;
☐ 11 conference papers as the first author are published/orally presented (partially invited), including 3 on IEDM, the flagship conferences in the field of microelectronics, and 1 on Symposium on VLSI, as well as on NSREC and RADECS, the top-level conferences on integrated circuit radiation effects. Multiple reports received reports from European semiconductor media, as well as positive interviews from senior editor of IEEE Spectrum magazine. 1 highlight paper and technical key paper at the Symposium on VLSI 2022 conference. Massive attention are obtained from world famous semiconductor companies such as Intel, Qualcomm, Samsung, TSMC, as well as top universities such as Stanford University, being specially invited to give technical reports and getting high praise.
Journal Articles | 期刊文章
[J14] R. Chen*. “Pushing carbon nanotube circuits below the 10-nm node,” Nature Electronics, 473–474 (2023). https://doi.org/10.1038/s41928-023-00986-0
[J13] R. Chen*, et al., “Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances—Part I: Pristine MWCNT,” IEEE Transactions on Electron Devices, Vol. 65, No. 11, pp. 4955-4962, Nov. 2018.
[J12] R. Chen*, et al., “Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances—Part II: Impact of Charge Transfer Doping,” IEEE Transactions on Electron Devices, Vol. 65, No. 11, pp. 4963-4970, Nov. 2018.
[J11] R. Chen*, et al., “Carbon Nanotube SRAM in 5 nm Technology Node Design, Optimization and Performance Evaluation-Part I: CNFET transistor optimization,” IEEE Transactions on VLSI Systems, Vol. 30, No. 4, pp. 432-439, Feb. 2022; DOI: 10.1109/TVLSI.2022.3146125
[J10] R. Chen*, et al., “Carbon Nanotube SRAM in 5 nm Technology Node Design, Optimization and Performance Evaluation-Part II: CNT interconnect optimization,” IEEE Transactions on VLSI Systems, Vol. 30, No. 4, pp. 440-448, Feb. 2022; DOI: 10.1109/TVLSI.2022.3146064
[J09] R. Chen*, et al., “Effects of total-ionizing-dose irradiation on SEU- and SET-induced soft errors in bulk 40-nm sequential circuits,” IEEE Transactions on Nuclear Science, Vol. 64, No. 1, pp. 471-476, January 2017.
[J08] R. Chen*, et al., “Effects of temperature and supply voltage on SEU- and SET-induced single-event errors in bulk 40-nm sequential circuits,” IEEE Transactions on Nuclear Science, Vol. 64, No. 8, pp. 2122-2128, Aug. 2017.
[J07] R. Chen*, et al., “Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits,” IEEE Transactions on Nuclear Science, Vol. 64, No. 8, pp. 2098-2106, Aug. 2017.
[J06] R. Chen*, et al., “Single-event multiple transients in conventional and guard-ring hardened inverter chains under pulsed-laser and heavy ion irradiation,” IEEE Transactions on Nuclear Science, Vol. 64, No. 9, pp. 2511-2518, Sep. 2017.
[J05] R. Chen*, et al., “Analysis of Temporal Masking Effects in Master and Slave Type Flip-Flop SEUs and Related Applications,” IEEE Transactions on Nuclear Science, Vol. 65, No. 8, pp. 1823-1829, Aug. 2018.
[J04] R. Chen*, et al., “Improved on-chip self-triggered single-event transient measurement circuit design and applications,” Microelectronics Reliability, Vol. 77, pp. 99-105, Apr. 2017.
[J03] Wen Zhao, Chaohui He, Wei Chen, R. Chen*, et al., “Single-event Double Transients in Inverter Chains Designed with Different Transistor Widths,” IEEE Transactions on Nuclear Science, Vol. 66, No. 7, pp. 1491-1499, May 2019.
[J02] Wen Zhao, Chaohui He, Wei Chen, R. Chen*, et al., “Single-Event Multiple Transients in Guard-ring Hardened Inverter Chains of Different Layout Designs,” Microelectronics Reliability, Vol. 87, pp. 151-157, Agu. 2018.
[J01] Wen Zhao, Chaohui He, Wei Chen, R. Chen*, et al., Mitigating single-event multiple transients in a combinational circuit based on standard cells,” Microelectronics Reliability, Vol. 109, pp. 113649, Jun. 2020.
Only journal articles published by Prof.Chen as the first author or corresponding author are included. (* for corresponding author)
Conference Papers | 会议文章
[C12] Feifan Xie, R. Chen*, et al., “Thermal mitigation strategy for backside power delivery network,” 2024 IEEE Electronic Components and Technology Conference (ECTC)
[C11] R. Chen, et al., “Invited Paper: Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection,” 2022 ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP). (Invited Reports)
[C10] R. Chen, et al., “Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed
with Back-side Power Delivery Network,” 2022 IEDM. (Interviews accepted：IEEE Spectrum: https://spectrum.ieee.org/interconnect-back-side-power)
[C09] R. Chen, et al., “Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node,” 2021 IEDM. (the work received highlights from IMEC and key reports from European semiconductor media such as eeNews and SILICON semiconductor)
[C08] R. Chen, et al., “3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes,” 2020 IEDM.
[C07] R. Chen, et al., “Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node,” 2022 Symposium on VLSI Technology and Circuits, June, Hawaii, USA. (the paper entered Technology Focus Session (9 papers in total), another co-author paperentered Highlight Session (5 papers in total))
[C06] R. Chen, et al., “Variability study of MWCNT interconnect, considering defects, contact resistance and impact of charge transfer doping,” DATE workshop, Dresden, 2017.
[C05] R. Chen, et al., “Effects of total-ionizing-dose irradiation on SEU- and SET-induced soft errors in bulk-40nm sequential circuits,” 2016 IEEE Nuclear and Space Radiation Effects Conference, Portland, Oregon, USA, July 11th, 2016. (Top international conference in the field of integrated circuit radiation effects, Oral Presentation, the only report from mainland China in 2016)
[C04] R. Chen, et al., “Effects of temperature and supply voltage on SEU- and SET-induced single-event errors in bulk 40-nm sequential circuits,” 2016 IEEE Conference on Radiation Effects on Components and Systems (RADECS), Bremen, Germany, pp. 1-4, Sep. 19th, 2016. (Top international conference in the field of integrated circuit radiation effects, Oral Presentation, the only report from mainland China in 2016)
[C03] R. Chen, et al., “Analysis of temporal masking effect on single-event upset rates for sequential circuits,” 2016 IEEE RADECS, Bremen, Germany, pp. 1-4, Sep. 19th, 2016. (Poster Presentation)
[C02] R. Chen, et al., “Analysis of temporal masking effect on SEUs of master-slave type flip-flops and related applications,” 2017 IEEE RADECS. (Poster Presentation)
[C01] R. Chen*, et al., “Single-event performance of differential Flip-Flop designs and hardening implication,” 22nd IEEE IOLTS, Spain, July 7th, pp. 221-226, 2016. (Oral Presentation)
Only conference papers published by Prof.Chen as the first author or corresponding author are included. (* for corresponding author)
Invited Reports | 邀请报告
1. “Back Side Metal Routing based SRAM Macro Design and Optimization”, Feb 10, 2021, Invited by Intel (The report received high praise from Intel technical staff)
2. “3D-optimized SRAM Memories for iN5/iN3: Update on Macro Design and Impact on Memory-on-Logic Systems”, Dec 16, 2020, Invited by Intel
3. “Back Side Metal Routing based SRAM Macro Design and Optimization”, Feb 16, 2021, Invited by Qualcomm
4. "Carbon Nanotube SRAM in 5 nm Technology Node Design, Optimization and Performance Evaluation”, May 12, 2022, Invited by Prof.H.S.Philip Wong, Stanford University
Patents | 专利
1. 陈荣梅 等，基于触发器链的逻辑电路单粒子效应测试与分析方法，专利号：CN106405385
2. 陈荣梅 等，一种片上自触发单粒子瞬态脉冲测量方法及系统，专利号：CN106443202
Books | 专著
《纳米体硅CMOS工艺逻辑电路单粒子效应研究》，清华大学出版社，2020.11，陈荣梅 著