论文发表 | Publication
☐ 发表包括 Nature Electronics、IEEE 系列国际期刊和会议论文60多篇；
☐ 发表14篇一作或者通讯作者的微电子、集成电路领域权威期刊文章，包括1篇 Nature Electronics，2篇 IEEE Transactions on Electron Devices，2篇 IEEE Transactions on Very Large Scale Integration Systems，6篇 IEEE Transactions on Nuclear Science (集成电路辐射效应领域顶级期刊)及3篇 Microelectronics Reliability(微电子可靠性领域知名期刊)；13篇共同作者 SCI 期刊文章发表（未列出）；
☐ 发表/口头报告(部分是邀请)11篇会议文章(一作)，包括微电子领域旗舰会议 IEDM 3篇和 Symposium on VLSI 1篇，以及集成电路辐射效应顶级会议 NSREC 和 RADECS 。同时获得两项发明专利，出版一本学术专著。工作曾受到欧洲半导体媒体的多次报道，IEEE Spectrum 杂志高级编辑正面采访报道，曾获评 Symposium on VLSI 2022 大会亮点文章、技术重点文章，获得世界知名半导体公司包括英特尔、高通、三星、台积电等以及顶尖大学包括斯坦福大学的关注，曾受到它们的特别邀请作技术报告，并得到高度评价。
期刊文章 | Journal Articles
[J14] R. Chen*. “Pushing carbon nanotube circuits below the 10-nm node,” Nature Electronics, 473–474 (2023). https://doi.org/10.1038/s41928-023-00986-0
[J13] R. Chen*, et al., “Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances—Part I: Pristine MWCNT,” IEEE Transactions on Electron Devices, Vol. 65, No. 11, pp. 4955-4962, Nov. 2018.
[J12] R. Chen*, et al., “Variability Study of MWCNT Local Interconnects Considering Defects and Contact Resistances—Part II: Impact of Charge Transfer Doping,” IEEE Transactions on Electron Devices, Vol. 65, No. 11, pp. 4963-4970, Nov. 2018.
[J11] R. Chen*, et al., “Carbon Nanotube SRAM in 5 nm Technology Node Design, Optimization and Performance Evaluation-Part I: CNFET transistor optimization,” IEEE Transactions on VLSI Systems, Vol. 30, No. 4, pp. 432-439, Feb. 2022; DOI: 10.1109/TVLSI.2022.3146125
[J10] R. Chen*, et al., “Carbon Nanotube SRAM in 5 nm Technology Node Design, Optimization and Performance Evaluation-Part II: CNT interconnect optimization,” IEEE Transactions on VLSI Systems, Vol. 30, No. 4, pp. 440-448, Feb. 2022; DOI: 10.1109/TVLSI.2022.3146064
[J09] R. Chen*, et al., “Effects of total-ionizing-dose irradiation on SEU- and SET-induced soft errors in bulk 40-nm sequential circuits,” IEEE Transactions on Nuclear Science, Vol. 64, No. 1, pp. 471-476, January 2017.
[J08] R. Chen*, et al., “Effects of temperature and supply voltage on SEU- and SET-induced single-event errors in bulk 40-nm sequential circuits,” IEEE Transactions on Nuclear Science, Vol. 64, No. 8, pp. 2122-2128, Aug. 2017.
[J07] R. Chen*, et al., “Impact of Temporal Masking of Flip-Flop Upsets on Soft Error Rates of Sequential Circuits,” IEEE Transactions on Nuclear Science, Vol. 64, No. 8, pp. 2098-2106, Aug. 2017.
[J06] R. Chen*, et al., “Single-event multiple transients in conventional and guard-ring hardened inverter chains under pulsed-laser and heavy ion irradiation,” IEEE Transactions on Nuclear Science, Vol. 64, No. 9, pp. 2511-2518, Sep. 2017.
[J05] R. Chen*, et al., “Analysis of Temporal Masking Effects in Master and Slave Type Flip-Flop SEUs and Related Applications,” IEEE Transactions on Nuclear Science, Vol. 65, No. 8, pp. 1823-1829, Aug. 2018.
[J04] R. Chen*, et al., “Improved on-chip self-triggered single-event transient measurement circuit design and applications,” Microelectronics Reliability, Vol. 77, pp. 99-105, Apr. 2017.
[J03] Wen Zhao, Chaohui He, Wei Chen, R. Chen*, et al., “Single-event Double Transients in Inverter Chains Designed with Different Transistor Widths,” IEEE Transactions on Nuclear Science, Vol. 66, No. 7, pp. 1491-1499, May 2019.
[J02] Wen Zhao, Chaohui He, Wei Chen, R. Chen*, et al., “Single-Event Multiple Transients in Guard-ring Hardened Inverter Chains of Different Layout Designs,” Microelectronics Reliability, Vol. 87, pp. 151-157, Agu. 2018.
[J01] Wen Zhao, Chaohui He, Wei Chen, R. Chen*, et al., Mitigating single-event multiple transients in a combinational circuit based on standard cells,” Microelectronics Reliability, Vol. 109, pp. 113649, Jun. 2020.
以上仅统计陈荣梅教授作为第一作者或通讯作者发表的文章。(* 代表通讯作者)
会议文章 | Conference Papers
[C12] Feifan Xie, R. Chen*, et al., “Thermal mitigation strategy for backside power delivery network,” 2024 IEEE Electronic Components and Technology Conference (ECTC)
[C11] R. Chen, et al., “Invited Paper: Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection,” 2022 ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP). (邀请报告)
[C10] R. Chen, et al., “Power, Performance, Area and Thermal Analysis of 2D and 3D ICs at A14 Node Designed
with Back-side Power Delivery Network,” 2022 IEDM. (接受采访：IEEE Spectrum: https://spectrum.ieee.org/interconnect-back-side-power)
[C09] R. Chen, et al., “Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node,” 2021 IEDM. (国际电子器件大会，工作受到imec亮点介绍，受到欧洲半导体媒体eeNews, SILICON semiconductor等重点报道)
[C08] R. Chen, et al., “3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes,” 2020 IEDM. (国际电子器件大会)
[C07] R. Chen, et al., “Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node,” 2022 Symposium on VLSI Technology and Circuits, June, Hawaii, USA. (国际超大规模集成电路会议，论文已经接受，论文进入大会Technology Focus Session (总共9篇)，另有一篇共同作者论文进入大会Highlight Session (总共5篇))
[C06] R. Chen, et al., “Variability study of MWCNT interconnect, considering defects, contact resistance and impact of charge transfer doping,” DATE workshop, Dresden, 2017.
[C05] R. Chen, et al., “Effects of total-ionizing-dose irradiation on SEU- and SET-induced soft errors in bulk-40nm sequential circuits,” 2016 IEEE Nuclear and Space Radiation Effects Conference, Portland, Oregon, USA, July 11th, 2016. (集成电路辐射效应领域顶级国际会议，口头报告，2016年大陆唯一一个报告)
[C04] R. Chen, et al., “Effects of temperature and supply voltage on SEU- and SET-induced single-event errors in bulk 40-nm sequential circuits,” 2016 IEEE Conference on Radiation Effects on Components and Systems (RADECS), Bremen, Germany, pp. 1-4, Sep. 19th, 2016. (集成电路辐射效应领域顶级国际会议，口头报告，2016年大陆唯一一个报告)
[C03] R. Chen, et al., “Analysis of temporal masking effect on single-event upset rates for sequential circuits,” 2016 IEEE RADECS, Bremen, Germany, pp. 1-4, Sep. 19th, 2016. (海报展示)
[C02] R. Chen, et al., “Analysis of temporal masking effect on SEUs of master-slave type flip-flops and related applications,” 2017 IEEE RADECS. (海报展示)
[C01] R. Chen*, et al., “Single-event performance of differential Flip-Flop designs and hardening implication,” 22nd IEEE IOLTS, Spain, July 7th, pp. 221-226, 2016. (口头报告)
以上仅统计陈荣梅教授作为第一作者或通讯作者发表的文章。(* 代表通讯作者)
邀请报告 | Invited Reports
1. “Back Side Metal Routing based SRAM Macro Design and Optimization”, 2021年02月10日, Intel公司邀请 (报告得到 Intel 技术人员高度评价)
2. “3D-optimized SRAM Memories for iN5/iN3: Update on Macro Design and Impact on Memory-on-Logic Systems”, 2020年12月16日, Intel 公司邀请
3. “Back Side Metal Routing based SRAM Macro Design and Optimization”, 2021年02月16日, Qualcomm公司邀请
4. "Carbon Nanotube SRAM in 5 nm Technology Node Design, Optimization and Performance Evaluation”, 2022年5月12日, 斯坦福大学 H.S.Philip Wong 教授邀请